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ICS91305 Datenblatt(PDF) 5 Page - Integrated Circuit Systems

Teilenummer ICS91305
Bauteilbeschribung  High Performance Communication Buffer
PDF  8 Pages
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Hersteller  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS91305 Datenblatt(HTML) 5 Page - Integrated Circuit Systems

  ICS91305 Datasheet HTML 1Page - Integrated Circuit Systems ICS91305 Datasheet HTML 2Page - Integrated Circuit Systems ICS91305 Datasheet HTML 3Page - Integrated Circuit Systems ICS91305 Datasheet HTML 4Page - Integrated Circuit Systems ICS91305 Datasheet HTML 5Page - Integrated Circuit Systems ICS91305 Datasheet HTML 6Page - Integrated Circuit Systems ICS91305 Datasheet HTML 7Page - Integrated Circuit Systems ICS91305 Datasheet HTML 8Page - Integrated Circuit Systems  
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ICS91305
0092G—08/06/07
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded
than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause
them to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations



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