ICS83905 datasheet(13/19 Pages) IDT

13 / 19 page

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

ICS83905AM REV. B JULY 9, 2007

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

LAYOUT GUIDELINE

Figure 5 shows an example of ICS83905 application schematic.

In this example, the device is operated at V

DD = 3.3V and VDDO =

3.3V. The decoupling capacitors should be located as close as

possible to the power pins. The input is driven by an 18pF load

resonant quartz crystal. The tuning capacitors (C1, C2) are fairly

VDD

.1uF

VDDO

ENABLE 2

100

Zo = 50 Ohm

VDD = 3.3V

15pf

VDD

15pF

LVCMOS

ENABLE 1

CL = 18 pf

Optional Termination

100

.1uF

LVCMOS

Zo = 50 Ohm

VDDO

ICS83905

XTAL_OUT

ENABLE 2

GND

BCLK0

VDDO

BCLK1

GND

BCLK2

VDD

BCLK3

GND

BCLK4

VDDO

BCLK5

ENABLE 1

XTAL_IN

10uF

VDDO = 3.3V

Unused outputs can be left floating. There should be

no trace attached to unused outputs. Device

characterized and specification limits set with all

outputs terminated.

.1uF

accurate, but minor adjustments might be required. For the

LVCMOS output drivers, two termination examples are shown in

the schematic. For additional termination, examples are shown

in the LVCMOS Termination Application Note.

FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT

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