P4C189 datasheet(3/8 Pages) PYRAMID

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P4C189

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Document # SRAM100 Rev OR

addressed word is read out on the inverting outputs (O

through O

3). The outputs of the memory go to an inactive

high impedance state whenever chip select (CS) is HIGH,

or during the write operation when write enable (WE) is

LOW.

An active LOW write enable (WE) controls the writing/

reading operation of the memory. When chip select (CS)

and write enable (WE) are LOW, the information on data

inputs (D

0 through D3) is written into the addressed memory

word. Reading is performed with chip select (CS) LOW and

write enable (WE) HIGH. The information stored in the

FUNCTIONALDESCRIPTION

Notes: H = HIGH

L = Low

X = Don't Care

HIGH Z = Implies outputs are disabled or off. This condition

is defined as high impedance state.

Mode

Output

Standby

High Z

Read

OUT

Write

High Z

TRUTH TABLE

TIMING WAVEFORM OF READ CYCLE NO. 1(5)

Sym.

Read Cycle Time

Chip Enable Access Time

Output Hold from Address Change

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

-35

Unit

AC CHARACTERISTICS—READ CYCLE

CC = 5V ± 10%, All Temperature Ranges)

(2)

Min

Max

Parameter

Address Access Time

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