P4C422 datasheet(3/10 Pages) PYRAMID

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P4C422

Page 3 of 10

Document # SRAM101 REV. A

Mode

Output

Standby

High Z

Standby

High Z

OUT Disabled

High Z

Read

OUT

Write

High Z

recovery times by eliminating the “write recovery glitch.”

Reading is performed with chip selct one (CS

1) LOW, chip

select two (CS

2) HIGH, write enable

(WE) HIGH and

output enable (OE) LOW. The information stored in the

addressed word is read out on the noninverting outputs

0 through O3). The outputs of the memory go to an

inactive high impedance state whenever chip select one

(CS

1) is HIGH, or during the write operation when write

enable (WE) is LOW.

An active LOW write enable (WE) controls the writing/

reading operation of the memory. When the chip select

one (CS

1) and the write enable (WE) are LOW and the chip

select two (CS

2) is HIGH, the information on data inputs

0 through D3) is written into the addressed memory word

and preconditions the output circuitry so that true data is

present at the outputs when the write cycle is complete.

This preconditioning operation insures minimum write

FUNCTIONAL DESCRIPTION

TRUTH TABLE

AC ELECTRICAL CHARACTERISTICS—READ CYCLE

CC = 5V ± 10% except as noted, All Temperature Ranges)

(2)

TIMING WAVEFORM OF READ CYCLE

Notes:

= HIGH

= Low

= Don't Care

HIGH Z = Implies outputs are disabled or off. This condition

is defined as high impedance state for the

P4C422.

Sym.

ACS

ZRCS

AOS

ZROS

Read Cycle Time (5)

Chip Select Time (5)

Chip Select to High-Z (6)

Output Enable Time

Output Enable to High-Z (6)

Address Access Time (5)

-10*

Min Max

7.5

-12

Min

Max

-15

Min

Max

-20

Min

Max

-25

Min

Max

-35

Min

Max

Unit

CC = 5V ± 5%

Parameter

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