IDT7130LA55PG datasheet(14/19 Pages) IDT

14 / 19 page

IDT7130SA/LA and IDT7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(2)

NOTES:

PLCC, TQFP and STQFP package only.

'X' in part numbers indicates power rating (SA or LA).

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform by BUSY Arbitration Controlled

by Address Match Timing(1)

tAPS

ADDR

'A'

AND 'B'

ADDRESSES MATCH

tBAC

tBDC

CE'B'

CE'A'

BUSY'A'

2689 drw 14

(2)

BUSY'B'

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

tAPS

ADDR'A'

ADDR'B'

2689 drw 15

(2)

tBAA

tBDA

tRC OR tWC

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisified, the

BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).

7130X20(1)

7140X20(1)

Com'l Only

7130X25

7140X25

Com'l, Ind

& Military

7130X35

7140X35

Com'l

& Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

tAS

Address Set-up Time

____

tWR

Write Recovery Time

____

tINS

Interrupt Set Time

____

tINR

Interrupt Reset Time

____

2689 tbl 12a

IDT7130LA55PG Datenblatt(PDF) 14 Page - Integrated Device Technology

IDT7130LA55PG Datenblatt(HTML) 14 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Datenblatt Download

Link URL