WM8213SCDR datasheet(21/38 Pages) WOLFSON

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Production Data

WM8213

PD Rev 4.0 July 2007

CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT

The following equations describe the processing of the video and reset level signals through the

WM8213. The values of V1, V2 and V3 are often calculated in reverse order during device setup. The

PGA value is written first to set the input Voltage range, the Offset DAC is then adjusted

to compensate for any Black/Reset level offsets and finally the RLC DAC value is set to position the

reset level correctly during operation.

Note:

Refer to Applications Note WAN0123 for detailed information on device calibration

procedures.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the

input video.

VIN - VRESET

Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

VIN - VVRLC

Eqn. 2

If VRLCDACPD = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.

If VRLCDACPD = 0, VVRLC is the output from the internal RLC DAC.

VVRLC

(VRLCSTEP

∗ RLC DAC[3:0]) + VRLCBOT

Eqn. 3

VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

The resultant signal V1 is added to the Offset DAC output.

V1 + {260mV

∗ (DAC[7:0]-127.5) } / 127.5

Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain.

∗ (0.66 + PGA[8:0]x7.34/511)

Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 16-bit unsigned number, with input range configured by

PGAFS[1:0].

D1[15:0] = INT{ (V3 /VFS)

∗ 65535} + 32767

PGAFS[1:0] = 00 or 01

Eqn. 6

D1[15:0] = INT{ (V3 /VFS)

∗ 65535}

PGAFS[1:0] = 11

Eqn. 7

D1[15:0] = INT{ (V3 /VFS)

∗ 65535} + 65535

PGAFS[1:0] = 10

Eqn. 8

where the ADC full-scale range, VFS = 2V when LOWREFS=0 and VFS = 1.2V when LOWREFS=1.

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

D2[15:0] = D1[15:0] (INVOP = 0)

Eqn. 9

D2[15:0] = 65535 – D1[15:0]

(INVOP = 1)

Eqn. 10

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