OPA607 datasheet(25/42 Pages) TI

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8.4.2 Layout Example

Place bypass capacitors

close to power pins

Place gain and feedback resistors

close to pins to minimize stray

capacitance

Place series output resistors

close to output pin to minimize

parasitic capacitance

Ground and power plane removed

from inner layers. Ground fill on

outer layers also removed

Ground and power plane exist on

inner layers.

Place bypass capacitors

close to power pins

Remove GND and Power plane

under output and inverting pins to

minimize stray PCB capacitance

CBYP

–

VS–

CBYP

VS+

Representative schematic

of a single channel

CBYP

Figure 8-4. Layout Recommendation for Dual-Channel DGK Package

Place bypass capacitors

close to power pins

Place gain and feedback resistors

close to pins to minimize stray

capacitance

Place series output resistors

close to output pin to minimize

parasitic capacitance

Ground and power plane removed

from inner layers. Ground fill on

outer layers also removed

Ground and power plane exist on

inner layers

Place bypass capacitors

close to power pins

Remove GND and Power plane

under output and inverting pins to

minimize stray PCB capacitance

CBYP

–

VS–

CBYP

VS+

Representative Schematic

of a Single Channel

CBYP

Thermal

Pad

Figure 8-5. Layout Recommendation for Dual-Channel DSN Package

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OPA863A, OPA2863A

SBOSA95F – MAY 2022 – REVISED OCTOBER 2024

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