LIS331DL datasheet(12/38 Pages) STMICROELECTRONICS

12 / 38 page

Mechanical and electrical specifications

LIS331DL

12/38

2.3.2

I2C interface

Subject to general operating conditions for Vdd and top.

Table 5.

I2C Slave timing values

Figure 5.

I2C slave timing diagram (4)

Note:

Data based on standard I2C protocol requirement, not tested in production

A device must internally provide an hold time of at least 300ns for the SDA signal (referred to

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL

Cb = total capacitance of one bus line, in pF

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port

Symbol

Parameter

I2C standard mode (1)

I2C fast mode (1)

Unit

Min

Max

Min

Max

f(SCL)

SCL clock frequency

100

400

KHz

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

3.45(2)

00.9(2)

µs

tr(SDA) tr(SCL)

SDA and SCL rise time

1000

20 + 0.1Cb

(3)

300

tf(SDA) tf(SCL)

SDA and SCL fall time

300

20 + 0.1Cb

(3)

300

th(ST)

START condition hold time

0.6

µs

tsu(SR)

Repeated START condition

setup time

4.7

0.6

tsu(SP)

STOP condition setup time

0.6

tw(SP:SR)

Bus free time between STOP

and START condition

4.7

1.3

SDA

SCL

tf(SDA)

tsu(SP)

tw(SCLL)

tsu(SDA)

tr(SDA)

tsu(SR)

th(ST)

tw(SCLH)

th(SDA)

tr(SCL)

tf(SCL)

tw(SP:SR)

START

REPEATED

START

STOP

START

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