Block Diagram

Note:

The address/data pins are available in various combinations (refer to the address/data table).

Pin Assignment

Latch Series

Momentary Series

Pin Description

Pin Name

I/O

Internal

Connection

Description

A0~A12

I

TRANSMISSION

GATE

Input pins for address A0~A12 setting

They can be externally set to VDD, VSS or left open.

D10~D17

O

CMOS OUT

Output data pins

DIN

I

CMOS IN

Serial data input pin

VT

O

CMOS OUT

Valid transmission, active high

OSC1

I

OSCILLATOR

Oscillator input pin

OSC2

O

OSCILLATOR

Oscillator output pin

VSS

¾¾

Negative power supply, ground

VDD

¾¾

Positive power supply

HT604L/HT614/HT692

Rev. 1.10

2

January 24, 2003

D a t a S h i f t

R e g i s t e r

O s c i l l a t o r

B u f f e r

S y n c . D e t e c t o r

D i v i d e r

C o m p a r a t o r

C o m p a r a t o r

B u f f e r

T r a n s m i s s i o n G a t e C i r c u i t

D a t a D e t e c t o r

C o n t r o l L o g i c

O S C 1

O S C 2

D I N

V D D

V S S

V T

D a t a

L a t c h C i r c u i t

A d d r e s s

H T 6 0 4 L

2 0 D I P - A / S O P - A

1 0 - A d d r e s s

4 - D a t a

A 1 1

D 1 2

D 1 3

D 1 4

D 1 5

V T

D I N

O S C 2

O S C 1

V S S

1

2

3

4

5

6

7

8

9

1 0

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

V D D

A 9

A 8

A 7

A 6

A 4

A 3

A 2

A 1

A 0

1 0 - A d d r e s s

4 - D a t a

H T 6 1 4

2 0 D I P - A / S O P - A

A 1 1

D 1 2

D 1 3

D 1 4

D 1 5

V T

D I N

O S C 2

O S C 1

V S S

1

2

3

4

5

6

7

8

9

1 0

V D D

A 9

A 8

A 7

A 6

A 4

A 3

A 2

A 1

A 0

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

H T 6 9 2

1 8 D I P - A

1 0 - A d d r e s s

2 - D a t a

A 1 1

A 1 2

D 1 4

D 1 5

V T

D I N

O S C 2

O S C 1

V S S

1

2

3

4

5

6

7

8

9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

V D D

A 9

A 8

A 7

A 6

A 3

A 2

A 1

A 0