HT46R321 datasheet(13/45 Pages) HOLTEK

13 / 45 page

HT46R321

Rev. 1.00

August 3, 2007

lar interrupt response takes place. If an interrupt request

flag is set to

²1² before entering the HALT mode, the

wake-up function of the related interrupt will be disabled.

Once a wake-up event occurs, it takes 1024 tSYS (sys-

tem clock period) to resume normal operation. In other

words, a dummy period will be inserted after wake-up. If

the wake-up results from an interrupt acknowledgment,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimise power consumption, all the I/O pins should

be carefully managed before entering the status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that resets only the program counter and stack

pointer, leaving the other circuits in their original state.

Some registers remain unchanged during other reset

conditions. Most registers are reset to the

²initial condi-

tion

² when the reset conditions are met. By examining

the PDF and TO flags, the program can distinguish be-

tween different

²chip resets².

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² means ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter Off

Input/Output Ports

Input mode

Stack Pointer

Points to the top of the stack

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

S y s t e m R e s e t

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

Reset Configuration

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

R E S

V D D

1 0 0 k W

1 0 k W

0 . 1 m F

0 . 0 1 m F

R E S

V D D

1 0 0 k W

0 . 1 m F

B a s i c

R e s e t

C i r c u i t

H i - n o i s e

R e s e t

C i r c u i t

Reset Circuit

Note: Most applications can use the Basic Reset Circuit

as shown, however for applications with extensive noise,

it is recommended to use the Hi-noise Reset Circuit.

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