HYB18H512321BF datasheet(10/43 Pages) QIMONDA

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HYB18H512321BF

512-Mbit GDDR3

Internet Data Sheet

Rev. 1.1, 2007-09

05292007-WAU2-UU95

2.4

Function Truth Table for CKE

TABLE 5

Function Truth Table II (CKE Table)

Notes

1. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the GDDR3 Graphics RAM immediately prior to clock edge n.

3. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND.

4. All states and sequences not shown are illegal or reserved.

5. DESEL or NOP commands should be issued on any clock edges occurring during the

XSR period. A minimum of 1000 clock

cycles is required before applying any other valid command.

11) During Action ACTIVE an ACT command on another banks is allowed considering

RRD . A PRE command on another bank is allowed any

time. WR, WR/A, RD and RD/A are always allowed.

12) During POWER DOWN and SELF REFRESH only the EXIT commands are allowed.

13) AUTO REFRESH starts with issuing the command and ends after

RFC.

14) Actions MODE REGISTER SET and EXTENDED MODE REGISTER SET start with issuing the command and ends after

MRD.

15) Action POWER DOWN EXIT starts with issuing the command and ends after tXPN.

16) Action SELF REFRESH EXIT starts with issuing the command and ends after

XSC.

CKE

N-1

CKE

CURRENT STATE

COMMAND

ACTION

Power Down

Stay in Power Down

Self Refresh

Stay in Self Refresh

Power Down

DESEL or NOP

Exit Power Down

Self Refresh

DESEL or NOP

Exit Self Refresh 5

All Banks Idle

DESEL or NOP

Entry Precharge Power Down

Bank(s) Active

DESEL or NOP

Entry Active Power Down

All Banks Idle

Auto Refresh

Entry Self Refresh

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