HYB18L256160BCX-7.5 datasheet(10/48 Pages) QIMONDA

10 / 48 page

Data Sheet

Rev. 1.11, 2007-01

07142005-CR47-RB2E

HY[B/E]18L256160B[C/F]X-7.5

256-Mbit Mobile-RAM

Functional Description

5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the

block.

2.2.1.2

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the

burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the

burst type and the starting column address, as shown in Table 5.

2.2.1.3

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and

the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock

edge n + m (for details please refer to the READ command description).

2.2.1.4

Write Burst Mode

When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write

accesses consist of single data elements only.

2.2.1.5

Extended Mode Register

The Extended Mode Register controls additional low power features of the device. These include the Partial Array

Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive

strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE

again or the device loses power.

The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified

time before initiating any subsequent operation. Violating either of these requirements result in unspecified

operation.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

EMR

Extended Mode Register

(BA[1:0] = 10B)

BA1

BA0

A12

A11

A10

A9A8

A7A6A5A4A3

A2A1A0

100

00000

(TCSR)

PASR

Field

Bits

Type Description

[6:5]

Selectable Drive Strength

Full Drive Strength

Half Drive Strength (default)

Note: All other bit combinations are RESERVED.

TCSR [4:3]

Temperature Compensated Self Refresh

Superseded by on-chip temperature sensor (see text)

HYB18L256160BCX-7.5 Datenblatt(PDF) 10 Page - Qimonda AG

HYB18L256160BCX-7.5 Datenblatt(HTML) 10 Page - Qimonda AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datenblatt Download

Link URL