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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ELANSC310 Datenblatt(PDF) 96 Page - Advanced Micro Devices |
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ELANSC310 Datenblatt(HTML) 96 Page - Advanced Micro Devices |
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96 / 119 page  96 Élan™SC310 Microcontroller Data Sheet PREL IMINARY Notes: For more information about DRAM first cycle write wait states, see the DRAM First Cycle Wait State Select Logic table in Chapter 4 of the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665. Notes: For more information about DRAM bank miss wait states, see the DRAM Bank Miss Wait State Select Logic table in Chapter 4 of the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665. Table 49. DRAM First Cycle Write Access (See Figure 39) Symbol Parameter Description Wait State Min Max Unit t5c D15–D0 setup to CAS Low (write) N/A 5 ns t27d MWE setup to CAS Low (first cycle) N/A 20 ns t30 MA valid setup to RAS Low N/A 0 ns t31 MA hold from RAS Low N/A 10 ns t32 MA setup to CAS Low N/A 0 ns t33 RAS hold from CAS Low N/A 20 ns t34 RAS precharge from CAS High N/A 10 ns t38 MA hold from CAS active N/A 15 ns t39 RAS to CAS delay N/A 20 ns t40 RAS pulse width N/A 70 10,000 ns t41d CAS pulse width (first cycle, write) 115 ns 245 375 ns t43 MWE hold from CAS Low N/A 15 ns t44d CAS hold from RAS Low (first cycle, write) 145 ns 275 ns 3 105 ns t49 D15–D0 hold from CAS Low (write) N/A 15 ns Table 50. DRAM Bank/Page Miss Write Cycles (See Figure 39) Symbol Parameter Description Wait State Min Max Unit t5c D15–D0 valid to CAS Low (write) N/A 5 ns t27c MWE to CAS Low 365 ns 465 ns 580 ns t29b CAS precharge N/A 60 ns t33 RAS hold from CAS Low 20 ns t34 RAS precharge from CAS High 10 ns t36 RAS precharge 338 ns 438 ns 553 ns t39 RAS to CAS delay N/A 20 ns t40 RAS pulse width N/A 70 10,000 ns t41c CAS pulse width (page miss write) 330 ns 460 ns 575 ns t44c CAS hold from RAS Low (page miss write) 360 ns 490 ns 5 105 ns t49 D15–D0 hold from CAS Low (write) N/A 15 ns |
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