This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

8

EN25P32

Rev. C, Issue Date: 2007/10/18

SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit is operated in conjunction with the Write

Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the

device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register

(SRP, BP2, BP1, BP0) become read-only bits.

In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal

sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,

the OTP sector is protected form program and erase operation. The OTP_LOCK bit can only be

programmed once.

Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,

user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR

command to lock the OTP sector before leaving OTP mode.

Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern the EN25P32

provides the following data protection mechanisms:

while the power supply is outside the operating specification.

Program, Erase and Write Status Register instructions are checked that they consist of a number of

clock pulses that is a multiple of eight, before they are accepted for execution.

All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the

Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:

–

Power-up

– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction

completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction

completion or Bulk Erase (BE) instruction completion or

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This

is the Software Protected Mode (SPM).

The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register

Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).

In addition to the low power consumption feature, the Deep Power-down mode offers extra software

protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored

except one particular instruction (the Release from Deep Power-down instruction).

Table 3 Protected Area Sizes Sector Organization

Status Register

Content

Memory Content

BP2

Bit

BP1

Bit

BP0

Bit

Protect Sectors

Addresses

Density(KB)

Portion

1

1

1

All

000000h-3FFFFFh

4096KB

All

1

1

0

Sector 32 to 63

200000h-3FFFFFh

2048KB

Upper 1/2

1

0

1

Sector 48 to 63

300000h-3FFFFFh

1024KB

Upper 1/4

1

0

0

Sector 56 to 63

380000h-3FFFFFh

512KB

Upper 1/8

0

1

1

Sector 60 to 63

3C0000h-3FFFFFh

256KB

Upper 1/16

0

1

0

Sector 62 to 63

3E0000h-3FFFFFh

128KB

Upper 1/32

0

0

1

Sector 63

3F0000h-3FFFFFh

64KB

Upper 1/64

0

0

0

None

None

None

None