ESS Technology, Inc.

SAM0575-021805

5

ES6218A PRODUCT BRIEF

ES6218A PIN DESCRIPTION

DCLK

105

I

Clock input to PLL.

UDAC

106

O

Video DAC output.

Y: Luma component for YUV and Y/C processing.

C: Chrominance signal for Y/C processing.

U: Chrominance component signal for YUV mode.

YUV0

O

YUV pixel 0 output data.

PIXOUT0

O

CCIR656 output pixel 0.

YUV1

107

O

YUV pixel 1 output data.

VREF

I

Internal voltage reference to video DAC. Bypass to ground with 0.1-

µF capacitor.

PIXOUT1

O

CCIR656 output pixel 1.

YUV2

108

O

YUV pixel 2 output data.

CDAC

O

Video DAC output. Refer to description and matrix for UDAC pin 106.

PIXOUT2

O

CCIR656 output pixel 2.

YUV3

109

O

YUV pixel 3 output data.

COMP

I

Compensation input. Bypass to ADVEE with 0.1-

µF capacitor.

PIXOUT3

O

CCIR656 output pixel 3.

YUV4

110

O

YUV pixel 4 output data.

RSET

I

DAC current adjustment resistor input.

PIXOUT4

O

CCIR656 output pixel 4.

Table 1

ES6218A Pin Description (Continued)

Name

Pin Numbers

I/O

Definition

Value

Y DAC

(pin 113)

C DAC

(pin 108)

U DAC

(pin 106)

0Y

C

N/A

1

Y

C

CVBS2

2Y

C

N/A

3

N/A

N/A

CVBS2

4

N/A

N/A

N/A

5

Y

Pb

Pr

6

Y

Pb

Pr

7G

B

R

8

Y

Pb

Pr

9G

B

R

10

G

R

B

11

G

R

B

12

Y

Pr

Pb

13

Y

Pr

Pb

14

G

R

B