7.5

Output capacitor selection

The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output

voltage ripple, which depends on the capacitor value and the equivalent resistive component (ESR). Therefore,

the output capacitor has to be selected in order to have a voltage ripple compliant with the application

requirements.

The voltage ripple equation can be calculated as:

∆VOUT=ESR∙∆IL_max+ ∆IL_max

8∙COUT∙FSW

(18)

For a ceramic (MLCC) capacitor, the capacitive component of the ripple dominates the resistive one. While for an

electrolytic capacitor the opposite is true. Neglecting the ESR contribution the minimum value of the output

capacitor is given by:

COUT_min_RIPPLE= ∆IL_max

8∙ΔVOUT∙FSW

(19)

As the compensation network is internal, the output capacitor should be selected in order to have a proper phase

margin and then a stable control loop.

7.6

Board layout guidelines

The DC-DC converter area is very sensitive, and it is necessary to pay attention to the layout of this part.

The DC-DC converter generates GND noise that can get coupled on the surrounding ground reducing the

sensitivity, and high-frequency components can be coupled onto the RF part. Therefore, to ensure a correct

layout, it is necessary to:

•

Provide efficient filtering by placing capacitors as close as possible

•

Reduce parasitic ensuring wide and short connections.

A two-layer or a four-layer board is strongly recommended. Put the ground layer very close to the top layer to

obtain a good ground plane reference. A minimum copper thickness for each layer of 0.035 mm (1 oz) is

suggested.

Put a ground plane internally to reduce the coupling between the traces. If it is not possible to use a four-layer

board, it is necessary to fill the area under the phase node of the board with ground metal to reduce or eliminate

radiation emissions.

Ground plane

Any switch-mode power supply requires a good PCB layout in order to achieve the maximum performance.

Component placement, and GND trace routing and width are the major issues. Basic rules commonly used for

DC-DC converters for good PCB layout should be followed. All traces carrying current should be drawn on the

PCB as short and as thick as possible. This should be done to minimize resistive and inductive parasitic effects

and increase system efficiency.

Connect all the ground metallization and/or layers with as many vias as possible. Ground vias between layers

should be added liberally throughout the RF portion of the PCB. This helps prevent the accrual of parasitic ground

inductance due to ground-current return paths. The vias also help to prevent cross-coupling from the RF and

other signal lines across the PCB.

Capacitor placing

Particular care has to be taken in the placement of the supply voltage filtering capacitors. It is, in fact, important to

ensure efficient filtering by placing these capacitors as close as possible from their dedicated pins.

The layout of decoupling capacitors is extremely important to minimize the induction loop formed between the

capacitor and the IC power and ground. The vias should be placed on the side of the capacitor lands, not the

ends. The vias should be located at the minimum keep-out distance and connected to the capacitor lands with a

wide trace - at least as wide as the via pad. Vias of opposite polarity should be placed as close together as

possible (minimum keep-out distance) and vias of the same polarity should be kept separated as much as

possible. If space allows, a second pair of vias on the opposite side of the capacitor may be added to reduce the

inductance further.

Inductor placing

The DC-DC converter inductor has to be placed as close as possible with traces as short and as thick as

possible. This should be done to minimize resistive parasitic effects and increase system efficiency.

DCP3601

Application information

DS14782 - Rev 1

page 13/26