TMP86CS49UG datasheet(63/252 Pages) TOSHIBA

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Page 49

TMP86CS49UG

5. I/O Ports

The TMP86CS49UG has 8 parallel input/output ports (56 pins) as follows.

Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external

input data should be externally held until the input data is read from outside or reading should be performed several

timer before processing. Figure 5-1 shows input/output timing examples.

External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This

timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-

gram.

Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O

port.

Note: The positions of the read and write cycles may vary, depending on the instruction.

Figure 5-1 Input/Output Timing (Example)

Primary Function

Secondary Functions

Port P0

8-bit I/O port

External interrupt, serial interface input/output, UART input/output.

Port P1

8-bit I/O port

External interrupt, timer counter input/output, divider output.

Port P2

3-bit I/O port

Low-frequency resonator connections, external interrupt input, STOP mode

release signal input.

Port P3

8-bit I/O port

Port P4

8-bit I/O port

Serial interface input/output and UART input/output.

Port P5

5-bit I/O port

Serial bus interface input/output.

Port P6

8-bit I/O port

Analog input and key-on wakeup input.

Port P7

8-bit I/O port

Analog input.

Data output

Data input

New

Old

Example: LD

A, (x)

Fetch cycle

Read cycle

Fetch cycle

Instruction execution cycle

Input strobe

(a) Input timing

Example: LD

(x), A

Fetch cycle

Write cycle

Fetch cycle

(b) Output timing

Instruction execution cycle

Output strobe

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