TMP86FH47ADUG datasheet(21/214 Pages) TOSHIBA

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Page 7

TMP86FH47ADUG

2. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.

This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86FH47ADUG memory is composed Flash, RAM, DBR(Data buffer register) and SFR(Special

function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86FH47ADUG

memory address map.

Figure 2-1 Memory Address Map

2.1.2 Program Memory (Flash)

The TMP86FH47ADUG has a 16384 bytes (Address C000H to FFFFH) of program memory (Flash ).

2.1.3 Data Memory (RAM)

The TMP86FH47ADUG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes

(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are

available against such an area.

SFR

0000H

64 bytes

SFR:

RAM:

Special function register includes:

I/O ports

Peripheral control registers

Peripheral status registers

System control registers

Program status word

Random access memory includes:

Data memory

Stack

003FH

RAM

0040H

512

bytes

023FH

DBR

0F80H

128

bytes

DBR:

Data buffer register includes:

Peripheral control registers

Peripheral status registers

0FFFH

C000H

Flash:

Program memory

Flash

16384

bytes

FFC0H

Vector table for vector call instructions

(32 bytes)

FFDFH

FFE0H

Vector table for interrupts

(32 bytes)

FFFFH

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