Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

Preview PDF HTML

STR750FV1 Datenblatt(PDF) 35 Page - STMicroelectronics

Teilenummer STR750FV1
Bauteilbeschribung  ARM7TDMI-S??32-bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
PDF  84 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STR750FV1 Datenblatt(HTML) 35 Page - STMicroelectronics

Back Button STR750FV1 Datasheet HTML 31Page - STMicroelectronics STR750FV1 Datasheet HTML 32Page - STMicroelectronics STR750FV1 Datasheet HTML 33Page - STMicroelectronics STR750FV1 Datasheet HTML 34Page - STMicroelectronics STR750FV1 Datasheet HTML 35Page - STMicroelectronics STR750FV1 Datasheet HTML 36Page - STMicroelectronics STR750FV1 Datasheet HTML 37Page - STMicroelectronics STR750FV1 Datasheet HTML 38Page - STMicroelectronics STR750FV1 Datasheet HTML 39Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 35 / 84 page
background image
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
35/84
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
5.3.3
Embedded voltage regulators
Subject to general operating conditions for VDD_IO, and TA
Table 11.
Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min(1)
1.
Data guaranteed by characterization, not tested in production.
Typ
Max(1)
Unit
tVDD_IO
VDD_IO rise time rate
20
µs/V
20
ms/V
tV18
V18 rise time rate
(1)
When 1.8 V power is supplied
externally
20
µs/V
20
ms/V
Table 12.
Embedded voltage regulators
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VMVREG
MVREG power supply(1)
1.
VMVREG is observed on the V18, V18REG and V18BKP pins except in the following case:
- In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2.
- In STANDBY mode. See note 2.
load <150 mA
1.65
1.80
1.95
V
VLPVREG
LPVREG power supply(2)
2.
In STANDBY mode, VLPVREG is observed on the V18BKP pin
In STOP mode, VLPVREG is observed on the V18, V18REG and V18BKP pins.
load <10 mA
1.30
1.40
1.50
V
tVREG_PWRUP
(1)
Voltage Regulators start-up
time (to reach 90% of final V18
value) at VDD_IO power-up
(3)
3.
Once VDD_IO has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET
during this start-up time.
VDD_IO rise
slope = 20 µs/V
80
µs
VDD_IO rise
slope = 20 ms/V
35
ms



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com