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T6LE2 Datenblatt(PDF) 7 Page - Toshiba Semiconductor |
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T6LE2 Datenblatt(HTML) 7 Page - Toshiba Semiconductor |
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7 / 12 page ![]() T6LE2 2006-09-20 7 Timing Diagram 1 (300-out mode, U/D = high level, MODE1 = high level, MODE2 = high level) Timing Diagram 2 (300-out mode, U/D = low level, MODE1 = high level, MODE2 = high level) DI/O (Input) CPVL/R 1 2 3 4 5 300 301 G1 G2 G3 G4 G300 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin XDON DO/I (Input) CPVL/R 1 2 3 4 5 300 301 G300 G299 G298 G297 G1 DI/O (Output) XDON high level OE L/R OE L/R : This part is output which is controlled ( fixed to VEE ) by OE pin |
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