TB62705CP/CF/CFN

2006-06-13

2

BLOCK DIAGRAM

TIMING DIAGRAM

Note:

Latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the CLOCK signal. The

data will pass through the latch circuit if the latch input is set at “H” level, and will be retained if the input is

set at “L”.

OUTn

OUTn

OUTn

SERIAL-IN

LATCH

CLOCK

OUT0

OUT1

OUT3

SERIAL-OUT

ENABLE

OUT7

5 V

0 V

5 V

0 V

Off

On

0 V

5 V

0 V

5 V

Off

On

Off

On

Off

5 V

0 V