Data Sheet

ADRF5030

THEORY OF OPERATION

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Rev. 0 | 11 of 13

The ADRF5030 integrates a driver to perform logic functions inter-

nally and to provide the advantage of a simplified CMOS/LVTTL-

compatible control interface. There are two digital control input pins

(EN, CTRL) that determine which RF port is in the insertion loss

state and in the isolation state. See Table 7 for the control voltage

truth table.

When the EN pin is logic high, all RF paths are in isolation state

regardless of the logic state of the other pin. The RFx ports are

terminated to internal 50 Ω resistors, and RFC becomes reflective.

RF INPUT AND OUTPUT

The RF ports (RFC, RF1, and RF2) are DC-coupled to 0 V, and no

DC-blocking is required at the RF ports when the RF line potential

is equal to 0 V. The RF ports are internally matched to 50 Ω.

The ADRF5030 is bidirectional with equal power-handling capabili-

ties. The RF input signal can be applied to the RFC port or the

selected RFx throw port.

The insertion loss path conducts the RF signal between the select-

ed RFx throw port and the RFC (common) port. The isolation paths

provide high loss between the insertion loss path and the unselect-

ed RFx throw port. The unselected RFx port of the ADRF5030 is

non-reflective.

The power handling of the ADRF5030 derates with frequencies

below 100 MHz. See Figure 2 for derating of the RF power towards

lower frequencies.

POWER SUPPLY

The ADRF5030 requires a positive supply voltage to be applied to

the VDD pin and a negative supply voltage to the VSS pin. Bypassing

capacitors are recommended on the supply lines to minimize RF

coupling.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Apply digital control inputs. The relative order of the control

inputs is not important. However, powering the digital control

inputs before the VDD supply can inadvertently forward bias and

damage the internal ESD protection structures. To avoid this

damage, use a series 1 kΩ resistor to limit the current flowing

into the control pin. Use pull-up or pull-down resistors if the

controller is in a high impedance state after VDD is powered up

and the control pins are not driven to a valid logic state.

4. Apply RF input signal.

Table 7. Control Voltage Truth Table

Digital Control Input

RFx Paths

EN

CTRL

RF1 to RFC

RF2 to RFC

Low

Low

Isolation (off)

Insertion loss (on)

Low

High

Insertion loss (on)

Isolation (off)

High

Low or High

Isolation (off)

Isolation (off)