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Rev C, 4/27/2023

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FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Power-Up Sequence

When the voltage on the FS210/FS310’s digital and analog supply pins VDD and VDDA rises above the power-on reset trip

point, a power-up sequence is initiated. The device’s behavior varies depending on the logic level on the MODE pin at

power-on reset. If MODE = 1, the device completes a master-mode power-up sequence. If MODE = 0, the device completes

a slave-mode power-up sequence.

In both master-mode and slave-mode power-up sequences, the FS210/FS310 sets the ISPS status bit (bit 7 of the Interrupt

Mask/Status Register INTR) to 1 and drives the IRQZ pin low as soon as the VDD/VDDA voltage rises above the power-on

reset trip point. For the next approximately 2.5ms, the device performs an internal self-configuration routine.

In a master-mode power-up sequence, when the self-configuration routine is complete, the device, acting as an I2C master,

executes an I2C read access to an off-chip non-volatile memory device such as the M24C32S-FCU from ST Microelectronics,

wherein the contents of addresses [0x0000-0x01FF], [0x0400-0x041F], and [0x0880-0x088C] in the off-chip memory device

are copied into the same addresses in the FlexSenseTM device (PXC, CCFG, and miscellaneous configuration registers,

respectively). If this I2C read access is successful and if the data byte copied into the device’s SIG register ([0x088C]) is equal

to 0xAA, then the device sets its SIGV register ([0x088E]) to 0x0A. When the I2C read access is complete (whether successful

or not), the device releases the IRQZ pin, and the power-up sequence is complete.

In a slave-mode power-up sequence, the FS210/FS310 does not execute an I2C read access to an off-chip non-volatile

memory device, and the device releases the IRQZ pin as soon as the self-configuration routine is complete, indicating the

completion of the power-up sequence. In this case, the device’s PXC and CCFG registers are in random states and the rest

of the configuration registers contain their power-on default values at the completion of the power-up sequence.

Therefore, proper operation of the FS210/FS310 depends upon the loading of values into these registers consistent with

the system in which the device is deployed, via one or more I2C write accesses to the device from a bus master elsewhere in

the system.

Throughout the duration of the power-up sequence – i.e. while the device is driving the IRQZ pin low, external I2C write and

read accesses are prohibited, and any such I2C accesses are ignored by the device. I2C write and read accesses are accepted

by the device once the IRQZ pin is released at the end of the power-up sequence.

I2C Interface

The I2C interface is used to read from and write to the FS210/FS310’s registers. The device functions as a fast-mode (max

400 Kbit/s) slave device (except during a master-mode power-up sequence, when it functions as a master), according to the

I2C specification document, located at:

http://www.nxp.com/documents/user_manual/UM10204.pdf

The FlexSenseTM device, when in slave mode, includes all the mandatory features (START and STOP condition recognition,

acknowledgement, 7-bit slave address) and none of the optional slave-device features specified by the I2C standards. Both

I2C pins, SCL and SDA, are open-drain, and they both require off-chip external pullup resistors to VDD. The SCL pin is driven

by whichever device on the I2C bus is the bus master, and the SDA pin is driven by whichever device is transmitting a data

bit.

The figure below illustrates the transfer of data bits on the I2C bus.