| Datenblatt-Suchmaschine für elektronische Bauteile |
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LP8720 Datenblatt(PDF) 2 Page - Texas Instruments |
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LP8720 Datenblatt(HTML) 2 Page - Texas Instruments |
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2 / 26 page ![]() VBATT LDO2 VIN1 LDO3 LDO1 IRQ_N DEFSEL GND SDA SCL IDSEL LDO4 GNDB DVS FB VIN2 VINB SW EN LDO5 4 3 2 1 A B C D E LP8720 SNVS575B – JULY 2008 – REVISED MAY 2013 www.ti.com Device Pin Diagram (20-Bump DSBGA) Top View Figure 1. Package Number YZR002011A LP8720 PIN DESCRIPTIONS(1) Pin Number Name Type Description A4 VBATT P Battery Input for LDO1 and all internal circuitry. E4 VINB P Battery Input for Buck. A2 VIN1 P Battery Input for LDO2 and LDO3. D1 VIN2 P Battery Input for LDO4 and LDO5. B4 LDO1 A LDO1 Output. A3 LDO2 A LDO2 Output. A1 LDO3 A LDO3 Output. C1 LDO4 A LDO4 Output. E1 LDO5 A LDO5 Output. E3 SW A Buck Output. D2 FB A Buck Feedback. D4 GNDB G Power Ground for Buck. B1 GND G IC Ground. C4 SDA DI/O I2C-compatible Serial Interface Data Input/Output. Open Drain output, external pull up resistor is needed, typ 1.5 k Ω. If not in use then hard wire to GND. C3 SCL DI I2C-compatible Serial Interface Clock input. External pull-up resistor is needed, typ 1.5 k Ω. If not in use then hard-wire to GND. B3 IRQ_N DO Interrupt output, active LOW. Open Drain output, external pull-up resistor is needed, typ 10 k Ω. If not in use then hard-wire to GND or leave floating. E2 EN DI Enable. EN=LO standby. EN=HI power on. Internal pull-down resistor 500 k Ω. If not in use then hard wire to VBATT. B2 DEFSEL DI Control input that sets the default voltages and startup sequence. Must be hard wired to BATT or GND or left floating (Hi-Z) for specific application. When DEFSEL= VBATT then setup 1 is used for default voltages and startup sequence. When DEFSEL= GND then setup 2 is used for default voltages and startup sequence. When DEFSEL= floating (Hi-Z) setup 3 is used for default voltages and startup sequence. C2 IDSEL DI Control input that sets the slave address for serial interface. Must be hard-wired to BATT or GND or left floating (Hi-Z) for specific application. When IDSEL= VBATT then slave address is 7h’7F. When IDSEL= floating (Hi-Z) then slave address is 7h’7C. When IDSEL= GND then slave address is 7h’7D. (1) A:Analog Pin D: Digital Pin I: Input Pin DI/O: Digital Input/Output Pin G:Ground Pin O: Output Pin P: Power Connection 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LP8720 |
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