LAN9252SLASHML datasheet(69/329 Pages) MICROCHIP

Teilenummer	LAN9252/ML

Bauteilbeschribung	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

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 2015 Microchip Technology Inc.

DS00001909A-page 69

LAN9252

9.4.4.1

Dual Phase Address Latching

The figures in this section detail read and write operations in multiplexed addressing mode with dual phase address

latching for 16 and 8-bit modes.

16-BIT READ

The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A read on

AD[15:0] follows. The cycle is repeated for the other 16-bits of the DWORD.

16-BIT READ WITH SUPPRESSED ALEHI

The address is latched sequentially from AD[7:0]. AD[15:8] is not used or driven for the address phase. A read on

AD[15:0] follows. The lower address is then updated to access the opposite WORD.

FIGURE 9-3:

MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READ

FIGURE 9-4:

MULTIPLEXED ADDRESSING WITH DUAL PHASE LATCHING - 16-BIT READ

WITHOUT ALEHI

ALELO

ALEHI

Address Low

Address High

Data 15:8

Data 7:0

Optional

Address+1 Low Address High

Data 31:24

Data 23:16

Optional

AD[15:8]

AD[7:0]

ALELO

ALEHI

Address Low

Address High

Data 15:8

Data 7:0

Optional

Address+1 Low

Data 31:24

Data 23:16

Optional

AD[15:8]

AD[7:0]

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