LAN9252TVSLASHML datasheet(59/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 59

LAN9252

8.3.2

INTERRUPT STATUS REGISTER (INT_STS)

This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt

conditions have been met, while a value of 0 indicates the interrupt conditions have not been met. The bits of this register

reflect the status of the interrupt source regardless of whether the source has been enabled as an interrupt in the Inter-

rupt Enable Register (INT_EN). Where indicated as R/WC, writing a 1 to the corresponding bits acknowledges and

clears the interrupt.

Offset:

058h

Size:

32 bits

Bits

Description

Type

Default

Software Interrupt (SW_INT)

This interrupt is generated when the Software Interrupt Enable

(SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) is set high.

Writing a one clears this interrupt.

R/WC

Device Ready (READY)

This interrupt indicates that the device is ready to be accessed after a

power-up or reset condition.

R/WC

RESERVED

PHY B Interrupt Event (PHY_INT_B)

This bit indicates an interrupt event from PHY B. The source of the interrupt

can be determined by polling the PHY x Interrupt Source Flags Register

(PHY_INTERRUPT_SOURCE_x).

PHY A Interrupt Event (PHY_INT_A)

This bit indicates an interrupt event from PHY A. The source of the interrupt

can be determined by polling the PHY x Interrupt Source Flags Register

(PHY_INTERRUPT_SOURCE_x).

25:23

RESERVED

21:20

RESERVED

GP Timer (GPT_INT)

This interrupt is issued when the General Purpose Timer Count Register

(GPT_CNT) wraps past zero to FFFFh.

R/WC

RESERVED

Power Management Interrupt Event (PME_INT)

This interrupt is issued when a Power Management Event is detected as

configured in the Power Management Control Register (PMT_CTRL). Writ-

ing a '1' clears this bit. In order to clear this bit, all unmasked bits in the

Power Management Control Register (PMT_CTRL) must first be cleared.

Note:

The Interrupt De-assertion interval does not apply to the PME

interrupt.

R/WC

16:13

RESERVED

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