TUSB2136 datasheet(36/53 Pages) TI

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2−23

2.9.4

Logical Interrupt Connection Diagram (INT0)

Figure 2−4 represents the logical connection of the interrupt sources and the relation of the logical connection with

INT0. The priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The

interrupt priorities are hard wired. Vector 46h is the highest and 12h is the lowest. Table 2−8 lists the interrupt source

for each valid interrupt vector.

Interrupts

INT0

Priority

Encoder

Vector

Interrupt Sources

46h

12h

Figure 2−4. Internal Vector Interrupt (INT0)

2.9.5

P2[7:0] Interrupt (INT1)

Figure 2−5 illustrates the conceptual port-2 interrupt. All port-2 input signals are connected in a logical OR to generate

the INT1 interrupt. Note that the inputs are active low and INT1 is programmed as a level-triggered interrupt. In

addition, INT1 is connected to the suspend/resume logic for remote wake-up support. As illustrated, the XINT bit in

the MCU configuration register (MCNFG) is used to select the EX1 interrupt source. When XINT = 0, P3.3 is the

source, and when XINT = 1, P2[7:0] is the source.

Suspend/

Resume

Logic

P2[7:0]

P3.3

INT1

XINT Bit

Figure 2−5. P2[7:0] Input Port Interrupt Generation

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