USBUF02W6 datasheet(5/11 Pages) STMICROELECTRONICS

5 / 11 page

USBUFxxW6

Technical information

5/11

Figure 6.

USBUFxxW6 ESD clamping behavior

Figure 7.

Measurement board

To have a good approximation of the remaining voltages at both Vin and Vout stages, we

give the typical dynamical resistance value Rd. By taking into account these following

hypothesis: Rt > Rd, Rg > Rd and Rload > Rd, it gives these formulas:

The results of the calculation done for Vg = 8 kV, Rg = 330 Ω (IEC 61000-4-2 standard),

VBR = 7 V (typ.) and Rd = 1 Ω (typ.) give:

Vinput = 31.2 V

Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also

important to note that in this approximation the parasitic inductance effect was not taken into

account. This could be few tenths of volts during few ns at the Vinput side. This parasitic

effect is not present at the Voutput side due the low current involved after the resistance Rt.

The measurements done hereafter show very clearly (figure 8) the high efficiency of the

ESD protection:

●

no influence of the parasitic inductances on Voutput stage

●

Voutput clamping voltage very close to VBR (breakdown voltage) in the positive way

and - VF (forward voltage) in the negative way

ESD Surge

Vinput

Voutput

Rload

Device

to be

protected

USBUF01W6

TEST BOARD

ESD

SURGE

16kV

Air

Discharge

Vin

Vout

Vinput

⋅

-----------------------------------------------

ouput

⋅

Vinput

⋅

-------------------------------------------------------

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