ADC14155LCVAL datasheet(4/36 Pages) TI2

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AGND

IDC

REF

AGND

ADC14155QML-SP

SNAS378L – NOVEMBER 2008 – REVISED FEBRUARY 2019

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Pin Descriptions and Equivalent Circuits

PIN NO.

SYMBOL

EQUIVALENT CIRCUIT

DESCRIPTION

ANALOG I/O

VIN–

Differential analog input pins. The differential full-scale input signal

level is two times the reference voltage with each input pin signal

centered on a common mode voltage, VCM.

VIN+

42, 43

VRP

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1-µF capacitor placed very close to

the pin to minimize stray inductance. A 0.1-µF capacitor should be

placed between VRP and VRN as close to the pins as possible, and a

10-µF capacitor should be placed in parallel.

VRP and VRN should not be loaded. VRM may be loaded to 1mA for

use as a temperature stable 1.5-V reference.

It is recommended to use VRM to provide the common mode voltage,

VCM, for the differential analog inputs, VIN+ and VIN–.

46, 47

VRM

44, 45

VRN

VREF

This pin can be used as either the 1-V internal reference voltage

output (internal reference operation) or as the external reference

voltage input (external reference operation).

To use the internal reference, VREF should be decoupled to AGND

with a 0.1-µF, low equivalent series inductance (ESL) capacitor. In

this mode, VREF defaults as the output for the internal 1.0-V

reference.

To use an external reference, overdrive this pin with a low noise

external reference voltage. The output impedance of the internal

reference at this pin is 9k

Ω. Therefore, to overdrive this pin, the

impedance of the external reference source should be << 9 k

Ω.

This pin should not be used to source or sink current.

The full scale differential input voltage range is 2 * VREF.

DIGITAL I/O

CLK+

The clock input pins can be configured to accept either a single-

ended or a differential clock input signal.

When the single-ended clock mode is selected through CLK_SEL/DF

(pin 8), connect the clock input signal to the CLK+ pin and connect

the CLK– pin to AGND.

When the differential clock mode is selected through CLK_SEL/DF

(pin 8), connect the positive and negative clock inputs to the CLK+

and CLK– pins, respectively.

The analog input is sampled on the falling edge of the clock input.

CLK–

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