Y1

24MHZ

R1

1M

CL1

18pF

CL2

18pF

TUSB8040 - CLOCK

XO

74

VSS_OSC

75

XI

76

Not Recommended for New Designs

TUSB8040

www.ti.com

SLLSE42I – SEPTEMBER 2010 – REVISED SEPTEMBER 2013

4

CLOCK GENERATION

The TUSB8040 accepts a crystal input to drive an internal oscillator or an external clock source. If a clock

is provided to XI instead of a crystal, XO is left open and VSSOSC should be connected to the PCB

ground plane. Otherwise, if a crystal is used, the connection needs to follow the guidelines below. Since XI

and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as

possible and away from any switching leads. It is also recommended to minimize the capacitance between

XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external capacitors CL1

and CL2 and shielding them with the clean ground lines. The VSSOSC should not be connected to PCB

ground when using a crystal.

Figure 4-1. TUSB8040 Clock

4.1

Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 pF - 24 pF and frequency stability

rating of ±100 PPM or better. To ensure proper startup oscillation condition, a maximum crystal equivalent

se-ries resistance (ESR) of 50

Ω is recommended. A parallel, 18-pF load capacitor should be used if a

crystal source is used. VSSOSC should not be connected to the PCB ground plane.

4.2

Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM

or better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak

to peak jitter after applying the USB 3.0 jitter transfer function. XI should be tied to the 1.8-V clock source

and XO should be left floating. VSSOSC should be connected to the PCB ground plane.

Copyright © 2010–2013, Texas Instruments Incorporated

CLOCK GENERATION

21

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