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DSD1796 Datenblatt(PDF) 28 Page - Texas Instruments |
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DSD1796 Datenblatt(HTML) 28 Page - Texas Instruments |
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28 / 63 page ![]() DSD1796 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com 28 ZFGx: Zero-Detection Flag Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Default value: 00 ZFGx = 0 Not zero ZFGx = 1 Zero detected When the DSD1796 detects that audio input data is continuously zero, the ZFGx bit is set to 1 for the corresponding channel(s). B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 23 R 0 0 1 0 1 1 1 RSV RSV RSV ID4 ID3 ID2 ID1 ID0 R: Read Mode Select Value is always 1, specifying the readback mode. ID[4:0]: Device ID The ID[4:0] bits hold a device ID in the TDMCA mode. |
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