SN74HC166AEP

8BIT PARALLELLOAD SHIFT REGISTER

SCLS559 − JANUARY 2004

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree†

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max ICC

D Typical tpd = 13 ns

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Synchronous Load

D Direct Overriding Clear

D Parallel-to-Serial Conversion

description/ordering information

This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding

clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high,

SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock

(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on

the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the

low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a

clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low

enables the other clock input. This allows the system clock to be free running, and the register can be stopped

on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.

CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

SOIC − D

Tape and reel

SN74HC166AIDREP

SHC166IEP

−40

°C to 85°C

TSSOP − PW

Tape and reel

SN74HC166AIPWREP§

SHC166IEP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

§ Product Preview

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SER

A

B

C

D

CLK INH

CLK

GND

VCC

SH/LD

H

QH

G

F

E

CLR

D OR PW PACKAGE

(TOP VIEW)

Copyright

 2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.