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t

fs

IN

OUT

0V

or

V

1

CC

V

1

CC

V

I

C

L

NOTEB

V

O

V

I

V

O

50%

V

1

CC

0V

V

OH

V

OL

2.7V

IN

OUT

GND1

NOTEB

S1

V

orV

OH

OL

V

1

CC

V

2

CC

C=0.1 F±1%

m

C=0.1 F±1%

m

GND2

Pass-failcriteria:

Outputmust

remainstable

OUT

Tektronix

HFS9009

PATTERN

GENERATOR

IN

DUT

Tektronix

784D

V

1

CC

0V

V

/ 2

C C

Jitter

ISO7240

ISO7241

ISO7242

SLLS868A – SEPTEMBER 2007 – REVISED DECEMBER 2007

PARAMETER MEASUREMENT INFORMATION (continued)

A.

B.

The input pulse is supplied by a generator having the following characteristics: PRR

Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms

A.

B.

The input pulse is supplied by a generator having the following characteristics: PRR

Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform

or 0s.

Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform

14

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Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): ISO7240 ISO7241 ISO7242