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f − Frequency − MHz

−120

−100

−80

−60

−40

−20

7.6

10.1

12.6

15.1

17.6

20.1

22.6

fdata = 122.88 MSPS

IF = 15.36 MHz

ACLR = 77.16 dB

Dual Bus Mode

G015

f − Frequency − MHz

−120

−100

−80

−60

−40

−20

23.0

25.5

28.0

30.5

33.0

35.5

38.0

fdata = 122.88 MSPS

IF = 30.72 MHz

ACLR = 72.7 dB

Dual Bus Mode

G016

DIGITAL INPUTS AND TIMING

Digital Inputs

DA[13:0]

DB[13:0]

SLEEP

CLKA/B

WRTA/B

Internal

Digital In

DVDD

DGND

DAC5672-EP

SGLS339A – JUNE 2006 – REVISED OCTOBER 2006

TYPICAL CHARACTERISTICS (continued)

POWER

POWER

vs

vs

FREQUENCY

FREQUENCY

Figure 16.

Figure 17.

The data input ports of the DAC5672 accept a standard positive coding with data bits DA13 and DB13 being the

most significant bits (MSBs). The converter outputs are specified to support a clock rate up to 200 MSPS. The

best performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle

may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within

their specified limits.

All digital inputs of the DAC5672 are CMOS compatible. Figure 18 and Figure 19 show schematics of the

equivalent CMOS digital inputs of the DAC5672. The 14-bit digital data input follows the offset positive binary

coding scheme. The DAC5672 is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.

Figure 18. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor

13

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