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INA821 Datenblatt(PDF) 17 Page - Texas Instruments |
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INA821 Datenblatt(HTML) 17 Page - Texas Instruments |
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17 / 22 page ![]() 8.4.2 Layout Example IN– 4 IN+ 1 2 3 DA_IN– OUT REF 9 DA_IN+ 12 11 10 PAD R2 GND IN+ R1 GND C4 C2 C7 C6 ADC_IN Use ground pours for shielding the input signal pairs Place bypass capacitors as close to IC as possible R3 C8 Consider using thermal vias for heatsinking Cutouts on ground planes underneath input pins can reduce stray capacitance, for better phase margin GND VS+ R2 R1 C2 PGA848 ADC IN REF OUT Connect feedback capacitors between OUT and DA_IN– (optional) A<2:0> DGND IN– A2 A0 C1 GND LVSS VS C5 VS+ LVDD Optional noise filtering capacitors C1 VS C6 C7 C8 R3 Connect feedback capacitors between REF and DA_IN+ (optional) C4 C5 C9 ADC_REF / 2 GND C9 ADC_REF / 2 VIN+ VIN VLVDD VLVSS Figure 8-6. Example Schematic and Associated PCB Layout www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: PGA848 |
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