STTS752E datasheet(31/38 Pages) STMICROELECTRONICS

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STTS75

DC and AC parameters

31/38

Figure 16.

Bus timing requirements sequence

Valid for ambient operating temperature: TA = –55 to 125°C; VDD = 2.7V to 5.5V (except where noted).

Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling

edge of SCL.

For SMBus compatibility STTS75 supports bus timeout. Holding the SDA line low for a period greater than

timeout duration will cause STTS75 to reset the SDA line to the state of serial bus communication (SDA

high).

Table 15.

AC characteristics

Sym

Parameter(1)

Min

Max

Unit

fSCL

SCL clock frequency

400

kHz

tBUF

Time the bus must be free before a new transmission can start

1.3

µs

SDA and SCL fall time

300

tHD:DAT

(2)

Data hold time

0.9

µs

tHD:STA

START condition hold time (after this period the first clock pulse is

generated)

600

tHIGH

Clock high period

600

tLOW

Clock low period

1.3

µs

SDA and SCL rise time

300

tSU:DAT

Data setup time

100

tSU:STA

START condition setup time (only relevant for a repeated start

condition)

600

tSU:STO

STOP condition setup time

600

tTIME-OUT SDA low time for reset of serial interface

(3)

325

AI00589

SDA

tSU:STO

tSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STA

tBUF

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