STM32WL33CB datasheet(16/91 Pages) STMICROELECTRONICS

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The radio block is able to generate two events to wake up the system through its embedded wake-up timer

running on low speed clock:

–

SUBG RFIP wakeup time is reached

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the LPAWUR RFIP is able to generate a wakeup event

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the LCD is able to generate a wakeup event

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the COMP is able to generate a wakeup event (with polarity selection, like I/Os)

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the RTC is able to generate a wakeup event

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the LC sensor controller is able to generate a wakeup event

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the LPUART is able to generate a wakeup event

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the IWDG is able to generate a reset event

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All I/Os are able to wake up the system.

At wakeup, the hardware resources located in the VDD12i power domain are reset, the CPU reboots. The reason

for wakeup is visible in a PWRC register.

3.6.3

Shutdown mode

The Shutdown mode is the least power consuming mode. The conditions to enter Shutdown mode are the same

conditions needed to enter Deepstop mode except that the PWRC_CR1.LPMS bit must be equal to 1.

(PWRC_DBGR.DEEPSTOP2 bit must be maintained equal to 0).

In Shutdown mode, the STM32WL33xx is in ultra-low power consumption: all voltage regulators, clocks and the

RF interface are not powered. The STM32WL33xx can enter shutdown mode by internal software sequence.

There are two ways to exit shutdown mode: by asserting and de-asserting the RSTN pin or by configurable pulse

polarity on GPIO PB0.

In Shutdown mode:

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The system is powered down as both the regulators are OFF

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The VDDIO power domain is ON

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All the clocks are OFF, LSI and LSE are OFF

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The I/O pull-ups and pull-downs can be controlled during Shutdown mode, depending on the software

configuration

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Two wake-up sources are available: a low pulse on the RSTN pin or a configurable pulse polarity on GPIO

PB0.

The exit from Shutdown is like a POR start up. The BOR feature can be enabled or disabled during Shutdown.

STM32WL33xx

Functional overview

DS14221 - Rev 5

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