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STA339BWS Datenblatt(PDF) 36 Page - STMicroelectronics |
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STA339BWS Datenblatt(HTML) 36 Page - STMicroelectronics |
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36 / 79 page ![]() Register description STA339BWS 36/79 DocID015276 Rev 9 Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. Figure 11. OCFG = 00 (default value) Table 44. Output configuration engine selection OCFG[1:0] Output configuration Config pin 00 2 channel (full-bridge) power, 2 channel data-out: 1A/1B 1A/1B 2A/2B 2A/2B LineOut1 3A/3B LineOut2 4A/4B Line Out Configuration determined by LOC register 0 01 2 (half-bridge), 1(full-bridge) on-board power: 1A 1A Binary 0 ° 2A 1B Binary 90° 3A/3B 2A/2B Binary 45° 1A/B 3A/B Binary 0° 2A/B 4A/B Binary 90° 0 10 2 channel (full-bridge) power, 1 channel FFX: 1A/1B 1A/1B 2A/2B 2A/2B 3A/3B 3A/3B EAPDEXT and TWARNEXT Active 0 11 1 channel mono-parallel: 3A 1A/1B w/ C3BO 45° 3B 2A/2B w/ C3BO 45° 1A/1B 3A/3B 2A/2B 4A/4B 1 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 2 Channel 1 LPF LineOut1 OUT3B LPF LineOut2 OUT4B OUT4A OUT3A Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 2 Channel 1 LPF LineOut1 OUT3B LPF LineOut2 OUT4B OUT4A OUT3A |
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