Medusa VPX3424

VPX3424 Datasheet

Page 2 of 4

07-01-2014

OpenVPX™

 Profile

The VPX3424 is compatible with a large number OpenVPX™ (VITA 65) slot and module

profiles, making it suitable for a wide range of high-performance applications.

Compatible SLT profiles:

Compatible MOD profiles:

MOD3-PAY-2F2T-16.2.5-3

MOD3-PER-2F-16.3.1-2

SLT3-PAY-2F2U-14.2.3

MOD3-PAY-2F2U-16.2.3-2

MOD3-PAY-1D-16.2.6-1

MOD3-PER-2F-16.3.1-3

SLT3-PAY-1F1F2U-14.2.4

MOD3-PAY-2F2U-16.2.3-3

MOD3-PAY-1D-16.2.6-2

MOD3-PER-1F-16.3.2-1

SLT3-PAY-2F2T-14.2.5

MOD3-PAY-1F1F2U-16.2.4-1

MOD3-PAY-2F-16.2.7-1

MOD3-PER-1F-16.3.2-2

SLT3-PAY-1D-14.2.6

MOD3-PAY-1F1F2U -16.2.4-2

MOD3-PAY-2F-16.2.7-2

MOD3-PER-1U-16.3.3-1

SLT3-PAY-2F-14.2.7

MOD3-PAY-1F1F2U -16.2.4-3

MOD3-PAY-2F-16.2.7-3

MOD3-PER-1U-16.3.3-2

SLT3-PAY-1F2U-14.2.12

MOD3-PAY-1F1F2U -16.2.4-4

MOD3-PAY-1F2U-16.2.11-1

MOD3-STO-2U-16.5.1-1

SLT3-STO-2U-14.5.1

MOD3-PAY-1F1F2U -16.2.4-9

MOD3-PAY-1F2U-16.2.11-2

MOD3-STO-2U-16.5.1-2

MOD3-PAY-1F1F2U -16.2.4-11

MOD3-PAY-1F2U-16.2.11-5

MOD3-PAY-2F2T-16.2.5-2

MOD3-PAY-1F2U-16.2.11-7

 Data Plane

As per the VITA 46.4 standard, two x4 lanes of Gen3 PCI Express® are available for high-

bandwidth data movement via the OpenVPX™ data plane; supporting data rates of up to

8Gbaud per lane.

These interfaces can be configured by software. They can be combined into a single x8 lane,

Gen2 PCI Express® interface. The first x4 lane can be reconfigured into a Serial RapidIO®

High-Bandwidth, Low-Latency interface, as per VITA 46.3; supporting Serial RapidIO® data

rates of up to 5Gbaud per lane.

Each link (FP) has its own PCIe controller, which can be individually configured. As a Root

Complex (RC) it uses downstream ports, as an End Point (EP) it uses upstream ports.

 Control Plane

The VPX3424 implements a Gigabit Ethernet control plane architecture. The VPX3424

supports up to four Ultra-Thin Pipes (1000BASE-KX) or up to two Thin Pipes (1000BASE-T) as

its control plane interfaces.

 User I/O

The User I/O pins on the VPX3424 are packed with high-speed interconnects and flexible I/O

solutions. Four 10Gigabit and two Gigabit Ethernet connections are available for fast links to

the T4240. Additionally, two USB, two SATA and two CAN ports are available on the User I/O

pins.

Up to 36 User I/O pins are available to a powerful user-programmable FPGA. Customers can

freely determine the functionality of these pins by expanding the FPGA’s firmware, which

can include additional fast interconnects.

 Utility Plane

The VPX3424 implements a system management infrastructure using the standard I

2C bus

and IPMI protocol, an on-board system management block implements the Intelligent

Platform Management Controller (IPMC) function.