M41T0

Operation

Doc ID 9105 Rev 7

11/23

2.3

WRITE mode

In this mode the master transmitter transmits to the M41T0 slave receiver. Bus protocol is

shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0'

(R/W = 0) is placed on the bus and indicates to the addressed device that word address An

will follow and is to be written to the on-chip address pointer. The data word to be written to

the memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41T0

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte (see

Figure 7).

Figure 7.

Slave address location

Figure 8.

READ mode sequence

AI00602

R/W

SLAVE ADDRESS

START

A

0

100

0

11

AI00899

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

S

SLAVE

ADDRESS