DocID6103 Rev 12

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M41T11

Operation

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2.3

Write mode

In this mode the master transmitter transmits to the M41T11 slave receiver. Bus protocol is

shown in Figure 11. Following the START condition and slave address, a logic '0' (R/W = 0)

is placed on the bus and indicates to the addressed device that word address An will follow

and is to be written to the on-chip address pointer. The data word to be written to the

memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41T11

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte.

2.4

Data retention mode

With valid VCC applied, the M41T11 can be accessed as described above with read or write

cycles. Should the supply voltage decay, the M41T11 will automatically deselect, write

protecting itself when VCC falls (see Figure 15).

Figure 11. Write mode sequence

AI00591

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS