9 Detailed Description

9.1 Overview

The REF20xx are a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The Section

9.2 section provides a block diagram of the basic band-gap topology and the two buffers used to derive the VREF

and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of

Q2. The difference of the two base emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is

forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2, which has a

negative temperature coefficient. The resulting band-gap output voltage is almost independent of temperature.

Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The resistors R1, R2

and R3, R4 are sized such that VBIAS = VREF / 2.

e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and VBIAS,

implemented during the final steps of manufacturing after the plastic molding process. This method minimizes

the influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is

implemented in the REF20xx to minimize the temperature drift and maximize the initial accuracy of both the VREF

and VBIAS outputs.

9.2 Functional Block Diagram

+

+

e-Trim

e-Trim

+

VREF

VBIAS

R3

R4

R1

R2

Q1

Q2

VBE1

VBE2

-

-

+

+

R5

R7

R6

9.3 Feature Description

9.3.1 VREF and VBIAS Tracking

Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter

(ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF20xx are generated from

the same band-gap voltage as shown in the Section 9.2 section. Hence, both outputs track each other over

the full temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (maximum). The tracking accuracy

increases to 6 ppm/°C (maximum) when the temperature range is limited to –40°C to 85°C. The tracking error is

calculated using the box method, as described by Equation 2:

DIFF(MAX)

DIFF (MIN)

6

REF

V

V

Tracking Error

10

(ppm)

V

Temperature Range

§

·

x

¨

¸

x

©

¹

(2)

where

•

‡

DIFF

REF

BIAS

V

V

2 V

www.ti.com

REF2025, REF2030, REF2033, REF2041

SBOS600E – JULY 2018 – REVISED FEBRUARY 2022

Copyright © 2022 Texas Instruments Incorporated

Submit Document Feedback

17

Product Folder Links: REF2025 REF2030 REF2033 REF2041