L99H92 datasheet(9/77 Pages) STMICROELECTRONICS

9 / 77 page

Figure 4. NRDY status bit and CPLOW flag

GADG120920220925SA

2.6

Gate drivers

2.6.1

Outputs driving signals (PWM/IN1 and DIR/IN2)

When the OUTE control bit is reset with the FSINB pin high, all the gate drivers are disabled and the turned on

MOSFETs are passively shut off through the internal resistance connected between gate and source of each

MOSFET (RGSHx and RGSLx). Regardless of the OUTE control bit value, when the FSINB pin is pulled low all

the MOSFETs are actively shut off by the gate drivers forced in sink switch mode.

Once the OUTE control bit is set and the FSINB pin is high, the external MOSFETs are driven by the input pins

PWM/IN1 and DIR/IN2. Both input pins, PWM/IN1 and DIR/IN2, have an internal pull-down current (IPWM_in and

IDIR_in) to put the outputs in a well-known condition in case any of the pins will no longer be driven by the

microcontroller. Depending on the value of the INPMODE control bit, the device can work as full-bridge driver or

dual half-bridge driver:

•

If INPMODE = 0 (default value), the device works in full-bridge mode. In this case the active full-bridge

diagonal, fixing the rotational direction of the motor is selected by DIR/IN2 input while the driving PWM

signal has to be applied to PWM/IN1 input.

Depending on the active free-wheeling enable control bit value (AFWE) and the freewheeling selection control bit

value (FWS), four different freewheeling strategies are available: active or passive and freewheeling on either

high-side or low-side MOSFETs. The DIR input pin sets the active diagonal. The AFWE control bit enables or

disables active free-wheeling and the FWS control bit sets the free-wheeling path (HS or LS).

Table 2. Truth table

Device in active mode with INPMODE=0 (FULL-BRIDGE MODE)

Inputs

Outputs (in case of no faults)

OUTE

bit

AFWE bit

FWS

bit

FSINB

DIR

PWM

HS1

LS1

HS2

LS2

0(1)

OFF

OFF(2)

OFF

L99H92

Gate drivers

DS14069 - Rev 4

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