TPS2500 datasheet(21/43 Pages) TI2

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DISS

AUX

USB

)

TPS2500, TPS2501

www.ti.com

SLVS886C – OCTOBER 2008 – REVISED AUGUST 2010

USB Capacitance

Connect the USB capacitance from USB to the reference ground plane. The USB capacitance is on the output of

the power switch and provides energy for transient load steps. The TPS2500 does not require any USB

capacitance for operation. Additional capacitance can be added on USB, but it is recommended to not exceed

220 mF to maintain adequate phase margin for the boost converter control loop. The combined output

capacitance on AUX and USB should not exceed 500 mF. USB applications require a minimum of 120 mF on

downstream-facing ports.

ILIM and FAULT Resistors

Connect the ILIM resistor from ILIM to the reference ground plane. The ILIM resistor programs the current-limit

threshold of the USB power switch (see the Programming the Current-Limit Threshold Resistor section). The

ILIM pin is the output of an internal linear regulator that provides a fixed 400-mV output. The recommended

nominal resistor value using 1% resistors on ILIM is 16.1 k

Ω ≤ RILIM ≤ 200 kΩ. This range should be adjusted

accordingly if 1% resistors are not used. Do not overdrive ILIM with an external voltage or connect directly to

GND. Connect the ILIM resistor as close to the TPS2500 as possible to minimize the effects of parasitics on

device operation. Do not add external capacitance on the ILIM pin. The ILIM pin should not be left floating.

Connect the FAULT resistor from the FAULT pin to an external voltage source such as VAUX or VIN. The FAULT

pin is an open-drain output capable of sinking a maximum current of 10 mA continuously. The FAULT resistor

should be sized large enough to limit current to under 10 mA continuously. Do not tie FAULT directly to an

external voltage source. The maximum recommended voltage on FAULT is 6.5 V. The FAULT pin can be left

floating if not used.

Power Dissipation

Power dissipation is an important consideration in any power device with integrated MOSFETs. Although there

are internal thermal sensors that disable the device in the event of an overtemperature condition, it is still good

design practice to calculate the maximum junction temperature and to maintain the maximum junction

temperature under the recommended maximum of 125 °C. There are many ways to approximate the junction

temperature of the device. One method is to calculate the junction temperature rise by multiplying the power

dissipation of the device by the thermal resistance of the device package. The absolute junction temperature is

approximated by the addition of the ambient temperature plus the calculated junction temperature rise: TJ = TA +

(PDISS × qJA) ≤ 125°C

where TA and TJ are in °C, qJA is in °C/W, and PDISS is in W.

The maximum ambient temperature is often an application-specific requirement, such as 85°C maximum. The

thermal resistance is mainly a function of the device package but is impacted by system-level considerations

such as layout, heatsinking from the surrounding copper pours, the number of board layers, copper thickness,

airflow, and surrounding power-dissipating devices (e.g., the power inductor). External equipment such as a

thermal camera can help assess the overall thermal performance of a design. The thermal resistance value of

41.6 °C/W from the Dissipation Ratings table can be used as an initial estimate. The power dissipation of the

device is the sum of the power dissipation in the boost converter plus the power dissipation in the USB power

switch. This can be approximated by:

where PDISS is in W, VAUX is in V, IAUX and IUSB are in A, h is the efficiency of the boost converter, and rUSB is

Ω. IAUX is the additional current powering auxiliary loads and does not include any current powering the USB

load. Efficiency can be approximated from the efficiency graphs in the Application Curves section. This approach

may be slightly pessimistic because it does not separate any power losses in the inductor from overall converter

efficiency.

Layout Recommendations

Layout is an important design step due to the high switching frequency of the boost converter. Careful attention

must be applied to the PCB layout to ensure proper function of the device and to obtain the specified

performance. Potential issues resulting from poor layout techniques include wider line and load regulation

tolerances, EMI noise issues, stability problems, and USB current-limit shifts. It is critical to provide a

low-impedance ground path that minimizes parasitic inductance. Wide and short traces should be used in the

high-current paths, and components should be placed as close to the device as possible.

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