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IMSA110 Datenblatt(PDF) 7 Page - STMicroelectronics |
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IMSA110 Datenblatt(HTML) 7 Page - STMicroelectronics |
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7 / 26 page ![]() Shifter -2 to 14 Shifter [8:0] Cascade Adder Rectifier Prescaler Byte select Min/max register Comparator GT/LT Over/undershoot count Over/undershoot buffer Min/max buffer LSR 64 x 32 bit RAM 8 6 USR 32 Y bus [26:22] [21:0] 32 DATA TRANSFORMATION UNIT 22 22 22 MUX 22 22 22 22 From MAC array negative overflow positive overflow Cascade input pads 1 Rounding 22 Control STATISTICS MONITOR 5 22 22 1 1 8 from BCR DATA NORMALIZER Zero data 22 MUX 22 1 Rounding Output Adder 22 22 8 8 6 [21:14] [7:0] MUX MUX 88 [13:8] [21:14] [7:0] 22 Clock cycle Cascade output pads 1 2 3 4 5 6 Over/under select (Isbs) 2 Figure 4 : Detailed Block Diagram of the Backend Post-processing Unit IMSA110 7/26 |
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