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CY2SSTU32866 Datenblatt(PDF) 7 Page - SpectraLinear Inc |
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CY2SSTU32866 Datenblatt(HTML) 7 Page - SpectraLinear Inc |
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7 / 24 page ![]() CY2SSTU32866 Rev 1.0, November 25, 2006 Page 7 of 24 D CLK R G2 RESET J1 CLK H1 CLK Parity Generator 11 11 D2 A2 PPO QERR D1−D6, D8−D13 D1−D6, D8−D13 LPS0 (internal node) D1−D6, D8-D13 11 PAR_IN G1 1 0 R CLK 2−Bit Counter A3, T3 VREF 0 1 C0 G6 C1 G5 LPS1 (internal node) CE D CLK R D CLK R D CLK R D CLK R 0 1 CE Q1A−Q6A, Q8A−Q13A 11 Q1B−Q6B, Q8B−Q13B 11 Q Q Q Q Q Figure 3. Parity logic Diagram for 1:2 register-B configuration (positive logic) C0=1, C1=1 |
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