CY28800

Rev 1.0, November 21, 2006

Page 7 of 15

SRC_STP Clarification

The SRC_STP signal is an asynchronous input used for clean

stopping and starting the DIFT/C outputs. This input can be

Active High or Active Low based on the strapped value of the

OE_INV input. The SRC_STP signal is a debounced signal in

that its state must remain unchanged during two consecutive

rising edges of DIFC to be recognized as a valid assertion or

deassertion. (The assertion and deassertion of this signal is

absolutely asynchronous.) In the case where the output is

disabled via OE control, the output will always be tri-stated

regardless of the SRC_STP Drive Mode register bit state.

Notes:

1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN is an undefined mode and not recommended. Operation in this mode may result in glitches

excessive frequency shifting.

2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input).

3. LOCK output is a latched signal that is reset with the assertion of PWRDWN or when VDD<1.8V.

4. Special care must be taken to ensure that no abnormal clock behavior occurs after the assertion PLL LOCK (i.e., overshoot/undershoot is allowed).

5. In PLL mode, if power is valid and PWRDWN is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid

input clocks are detected, valid power, PWRDWN deasserted with the PLL locked and stable, are the DIF outputs enabled.

6. In the case where OE is asserted low, the output will always be three-stated regardless of SRC_STP drive mode register bit state.

DIFC

DIFT

Tstable

<1 ms

PWRDWN

Tdrive_Pwrdwn#

<300 s, >200 mV

Figure 4. PWRDWN Deassertion Diagram, OE_INV = 1

Table 4. Buffer Power-up State Machine

State

Description

0

3.3V Buffer power off

1

After 3.3V supply is detected to rise above 1.8V–2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay

Buffer waits for PWRDWN deassertion (and a valid clock on the SRC_IN input if in PLL mode)

Outputs enabled for normal operation (PLL lock to the SRC_IN input is assured in PLL mode)

OE_INV

SRC_STP

DIFT

DIFC

0

1

Normal

Normal

0

0

Iref * 6 or Float

Low

1

1

Iref * 6 or Float

Low

1

0

Normal

Normal