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IS25LP02GJ-RHLA3 Datenblatt(PDF) 97 Page - Integrated Silicon Solution, Inc

Teilenummer IS25LP02GJ-RHLA3
Bauteilbeschribung  SERIAL FLASH MEMORY 166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  182 Pages
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Hersteller  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP02GJ-RHLA3 Datenblatt(HTML) 97 Page - Integrated Silicon Solution, Inc

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IS25LP02GJ
IS25WP02GJ
Integrated Silicon Solution, Inc.- www.issi.com
97
Rev.A
10/02/2025
8.20 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and Status
Register write protection features by writing “0”s or “1”s into BP3, BP2, BP1, BP0, and SRWD bits. Also WRSR
instruction allows the user to disable or enable quad operation by writing “0” or “1” into QE bit.
To write Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for
the device to accept Write Status Register (01h) instruction (Status Register bit WEL must equal 1).
Figure 8.48 Write Status Register Sequence In SPI Mode
Instruction = 01h
CE #
SCK
SI
SO
Data In
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
7
3
2
1
0
6
5
4
High Impedence
Figure 8.49 Write Status Register QPI Sequence
01h
0
1
Mode 3
Mode 0
2
3
7:4
3:0
CE#
SCK
IO[3:0]
Data In



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