MP9989

– FAST TURN-OFF INTELLIGENT RECTIFIER

MP9989 Rev. 1.1

www.MonolithicPower.com

9

8/27/2020

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© 2020 MPS. All Rights Reserved.

OPERATION

The

MP9989

supports

operation

in

discontinuous

conduction

mode

(DCM),

continuous conduction mode (CCM), and quasi-

resonant flyback converters. The control circuitry

controls the gate in forward mode and turns the

gate off when the synchronous rectification (SR)

MOSFET current drops to zero.

VDD Generation

SENSE is the input for the linear regulator, the

output of which is VDD. VDD supplies the

MP9989, and is regulated at 6.7V.

When SENSE is under 4.7V, a 40mA current

source from SENSE charges up VDD. When

SENSE is above 4.7V, the linear regulator’s

maximum charging current is limited at IVDD to

charge the external capacitor at VDD.

Start-Up and Under-Voltage Lockout (UVLO)

When VDD rises above 4.2V, the MP9989 exits

under-voltage lockout (UVLO) and is enabled.

Once VDD drops below 4.0V, the MP9989

enters sleep mode and VGS is kept low.

Turn-On Phase

When VDS drops to ~2V, a turn-on timer begins.

If VDS reaches the -80mV turn-on threshold from

2V within the slew rate detection time (~30ns),

the MOSFET is turned on after a turn-on delay

tD-ON (~20ns) (see Figure 2). If VDS crosses -

80mV after the timer ends, the gate voltage

remains off. This turn-on timer prevents the

MP9989 from falsely turning on due to ringing

from DCM and quasi-resonant operations.

Turn-On Blanking

The control circuitry contains a blanking function.

When the MOSFET turns on, the control circuit

ensures that the on state lasts for a specific

period of time. The turn-on blanking time is tB-ON

(~1.2µs) to prevent an accidental turn off due to

ringing. However, if VDS reaches 1.8V within the

turn-on

blanking

time,

VGS

is

pulled

low

immediately.

Conduction Phase

When VDS rises above the forward voltage drop,

VFWD (-40mV), according to the decrease of the

switching current, the MP9989 lowers the gate

voltage level to enlarge the on resistance of the

synchronous MOSFET.

-3mV

-80mV

2V

VDS

VGS

Turn-On

Delay

Turn-Off

Delay

Turn-On

Blanking

Driver Begi ns

to be Pulled

Down

Driver Turn

Off

2V

Turn-Off

Blanking

-40mV

Figure 2: Turn-On/Turn-Off Timing Diagram

With this control scheme, VDS is adjusted to be

around VFWD even when the current through the

MOSFET is fairly low. This function keeps the

driver voltage at a very low level when the

synchronous MOSFET is turned off, which

boosts the turn-off speed and is especially

important to CCM operation.

Turn-Off Phase

When VDS rises to trigger the turn-off threshold (-

3mV), the gate voltage is pulled to zero after a

short turn-off delay of tD-OFF (about 25ns) (see

Figure 2).

Turn-Off Blanking

After the gate driver (VGS) is pulled to zero by VDS

reaching the turn-off threshold (-3mV), a turn-off

blanking time is applied, during which the gate

driver signal is latched off. The turn-off blanking

is removed when VDS rises above VB-OFF (2V)

(see Figure 2).