CY7C4255
CY7C4265
Document #: 38-06004 Rev. *C
Page 2 of 22
Functional Description (continued)
The CY7C4255/65 provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost
Empty, Half Full, Almost Full, and Full. The Half Full flag
shares the WXO pin. This flag is valid in the stand-alone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
flags become synchronous if the VCC/SMODE is tied to VSS.
All configurations are fabricated using an advanced 0.5
µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Pin Configurations
TQFP/STQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
16
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
CY7C4255
CY7C4265
Selection Guide
7C4255/65-10
7C4255/65-15
7C4255/65-25
7C4255/65-35
Maximum Frequency (MHz)
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
Minimum Data or Enable Set-Up (ns)
3
4
6
7
Minimum Data or Enable Hold (ns)
0.5
1
1
2
Maximum Flag Delay (ns)
8
10
15
20
Active Power Supply
Current (ICC1) (mA)
Commercial
45
45
45
45
Industrial
50
50
50
50
CY7C4255
CY7C4265
Density
8K x 18
16K x18
Package
64-pin TQFP,
STQFP
64-pin TQFP,
STQFP
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